Assuming it makes it to market, a multi-tiled GPU– essentially several GPUs in a single plan– would be a significant achievement for Intel. GPUs are infamously bandwidth-hungry due to the requirement to shovel data around between cores, caches, and command frontends, which makes them non-trivial to split up in a chiplet/tiled style. Even if Intel can just use this type of multi-tile scalability for calculate workloads, that would have a significant influence on what kind of efficiency a single GPU package can obtain, and how future servers may be developed.

At last weeks Intel Architecture Day, Intels primary architect, Raja Koduri, briefly held up the smallest member of the companys forthcoming Xe-HP series of server CPUs, the one tile setup. Now, just a few days later on, he has actually upped the ante by displaying the largest, 4 tile setup.

Designed to be a scalable chip architecture, Xe-HP is set to be offered with one, 2, or four tiles. And while Intel has yet to disclose too much in the method of details on the architecture, based upon their packaging disclosures it looks like the business is utilizing their EMIB tech to wire up the GPU tiles, as well as the GPUs on-package HBM memory.

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